TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 656

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

22.3
On-board Programming of Flash Memory (Rewrite/Erase)
31-1
0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
Note:This register is initialized by cold reset.
−
SECBIT
Bit Symbol
(2)
31
23
15
0
0
0
7
0
-
-
-
-
Note 1: This command must be issued in the ready state. Issuing the command in the busy state may dis-
Note 2: The value varies depending on protection applied.
FCSECBIT (Security bit register)
R
R/W
Type
able both correct command transmission and further command input. To exit from the condi-
tion, execute system reset. System reset requires at least 0.5 μs regardless of the system
clock frequency. In this condition, it takes approx. 2 ms to enable reading after reset.
30
22
14
0
0
0
6
0
-
-
-
-
Read as 0.
Security bits
0:disabled
1:enabled
29
21
13
0
0
0
5
0
-
-
-
-
Page 632
28
20
12
0
0
0
4
0
-
-
-
-
27
19
11
Function
0
0
0
3
0
-
-
-
-
26
18
10
0
0
0
2
0
-
-
-
-
25
17
0
0
9
0
1
0
-
-
-
-
TMPM361F10FG
SECBIT
24
16
0
0
8
0
0
1
-
-
-