TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 659

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

Note:The protection bit erase command cannot erase by individual block.
Table 22-17 Protection Bit Programming Address Table
Block0
Block1
Block2
Block3
Block4
Block5
Block6
Block7
Block9
Block8
Block
Table 22-18 Protection Bit Erase Address Table
Block0 to 3
Block4 to 7
Block8 to 9
Block
Table 22-19 The ID-Read command's fourth bus write cycle ID address (IA) and
IA[15:14]
Protection bit
<BLPRO[0]>
<BLPRO[1]>
<BLPRO[2]>
<BLPRO[3]>
<BLPRO[4]>
<BLPRO[5]>
<BLPRO[6]>
<BLPRO[7]>
<BLPRO[9]>
<BLPRO[8]>
0y00
0y01
0y10
0y11
the data to be read by the following 32-bit data transfer command (ID)
<BLPRO[0:3]>
<BLPRO[4:7]>
<BLPRO[8:9]>
Protection bit
Address
[18]
0
0
0
0
0
0
0
0
1
1
Reserved
Page 635
ID[7:0]
0x98
0x5A
0x10
The seventh bus write cycle address
Address
The seventh bus write cycle address
[17]
Address [18]
0
0
0
0
1
1
1
1
0
0
0
0
1
Address
Fixed to
[16:11]
Manufacturer code
"0".
[18:17]
Device code
Macro code
Code
−
Address [17]
Address
[10]
0
1
0
0
0
1
1
0
0
1
1
0
0
Address
[9]
0
1
0
1
0
1
0
1
1
0
TMPM361F10FG