TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 89

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

7.1.2.4
(1)
(2)
Exception exit
When returning from an ISR, the CPU takes one of the following actions :
When returning from an ISR, the CPU performs the following operations :
Execution after returning from an ISR
Exception exit sequence
・ Tail-chaining
・ Returning to the last stacked ISR
・ Returning to the previous program
・ Pop eight registers
・ Load current active interrupt number
・ Select SP
tion has higher priority than all stacked exceptions, the CPU returns to the ISR of the pend-
ing exception.
iting one ISR and entering another. This is called "tail-chaining".
er priority than the highest priority pending exception, the CPU returns to the last stacked
ISR.
SP.
track which interrupt to return to.
Mode, SP can be SP_main or SP_process.
If a pending exception exists and there are no stacked exceptions or the pending excep-
In this case, the CPU skips the pop of eight registers and push of eight registers when ex-
If there are no pending exceptions or if the highest priority stacked exception is of high-
If there are no pending or stacked exceptions, the CPU returns to the previous program.
Pops the eight registers (PC, xPSR, r0 to r3, r12 and LR) from the stack and adjust the
Loads the current active interrupt number from the stacked xPSR. The CPU uses this to
If returning to an exception (Handler Mode), SP is SP_main. If returning to Thread
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