TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 40

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

2.3
Exceptions / Interruptions
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
Exceptions / Interruptions
Exceptions and interruptions are described in the following section.
[4:0]> bit of NVIC register. In this product, if read <INTLINESUM[4:0]> bit, "0x00" is read out.
for assigning a priority level in the interrupt priority registers and system handler priority registers.
the Systic timer. SysTick calibration register can set a calibration value to measure 10ms. In this product,
when 8MHz is input to X1 pin, calibration value is set to 0x9C4 which can measure 10ms. Additionally, if
this value is read as "0" both of <NOREF> bit and <SKEW> bit, it indicates that external reference clock
are available and the calibration value is accurate as 10ms.
rupt and Reset Control Register are set.
ror included in software.
able interrupt (NMI) or reset.
to software.
"0x0000_0000" is read out.
Number of Interrupt Inputs
Number of Priority Level Interrupt Bits
SysTick
SYSRESETREQ
LOCKUP
Auxiliary Fault Status register
The number of interrupt inputs can optionally be defined from 1 to 240 in the Cortex-M3 core.
TMPM361F10FG has 64 interrupt inputs. The number of interrupt inputs is reflected in <INTLINESNUM
The Cortex-M3 core can optionally configure then umber of priority level interrupt bits from 3 bits to 8 bits.
TMPM361F10FG has three priority level interrupt bits. The number of priority level interrupt bits is used
The Cortex-M3 core has a SysTick timer which can generate SysTick exception.
In the TMPM361F10FG, the clock that is input from X1 pin dividing by 32 is used as a count clock for
The Cortex-M3 core outputs SYSRESETREQ signal when <SYSRESETREQ> bit of Application Inter-
TMPM361F10FG provides the same operation when SYSRESETREQ signal are output.
When irreparable exception generates, the Cortex-M3 core outputs LOCKUP signal to show a serious er-
TMPM361F10FG does not use this signal. To return from LOCKUP status, it is necessary to use non-mask-
The Cortex-M3 core provides auxiliary fault status registers to supply additional system fault information
However, TMPM361F10FG is not defined this function. If auxiliary fault status register is read, always
Note:Do not reset with <SYSRESETREQ> in SLOW mode.
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