DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 12

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev. 3.00 Mar 21, 2006 page x of liv
Item
5.6 Interrupt Control
Modes and Interrupt
Operation
Table 5.4 Interrupt
Control Modes
5.6.5 DTC Activation
by Interrupt
7.2.8 DTC Vector
Register (DTVECR)
7.4 Location of
Register Information
and DTC Vector Table
Table 7.1 Interrupt
Sources, DTC Vector
Addresses, and
Corresponding DTCEs
8.1 Overview
Table 8.1 Port
Functions of
H8S/2140B,
H8S/2141B,
H8S/2145B, and
H8S/2148B
8.4.4 Pin Functions
Page
105
114
151
154
167
171
181
Revision (See Manual for Details)
Table amended
Description amended
… the DTCE bit of DTC's DTCER, and the DISEL bit of …
Description amended
… software activation interrupt.
DTVECR is initialized to H'00 at a reset and in hardware
standby mode.
Note 2 amended
Note: 2. Not supported by the H8S/2148B and H8S/2145B (5-V
version).
Description amended
… in addition to DDR, to control the on/off …
Note * amended
Note: * Not supported by the H8S/2148B and H8S/2145B (5-V
version).
• P37/D15/HDB7/SERIRQ * , ... , P30/D8/HDB0/LAD0 *
Note amended
Note: * Not supported by the H8S/2148B and H8S/2145B (5-V
version).
Description
Interrupt mask control is performed by
the I bit. Priority levels can be set with
ICR.
3-level interrupt mask control is
performed by the I and UI bits. Priority
levels can be set with ICR.

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