DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 198

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 6 Bus Controller (BSC)
6.6.2
As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin
can be used in the initial cycle (full access) of the burst ROM interface. For details, see section
6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle.
6.7
When this LSI accesses the external address space, it can insert a 1-state idle cycle (T
bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM with a long output floating time, and
high-speed memory and I/O interfaces.
If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle
cycle is inserted at the start of the write cycle.
Figure 6.16 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle
for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.16 (a),
with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and
the CPU write data. In figure 6.16 (b), an idle cycle is inserted, thus preventing data collision.
Rev. 3.00 Mar 21, 2006 page 142 of 788
REJ09B0300-0300
Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)
Wait Control
Idle Cycle
Address bus
(IOSE = 0)
Data bus
AS/IOS
RD
T
1
Full access
Read data
T
2
Only lower
Read data Read data
T
Burst access
1
address changes
T
1
I
) between