DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 480
DF2148BTE20
Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20
HD64F2148BTE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 480 of 847
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Section 16 I
16.3.5
ICCR controls the I
Bit
7
6
5
4
Rev. 3.00 Mar 21, 2006 page 424 of 788
REJ09B0300-0300
Bit Name
ICE
IEIC
MST
TRS
I
2
C Bus Control Register (ICCR)
2
C Bus Interface (IIC) (Optional)
Initial Value R/W
0
0
0
0
2
C bus interface and performs interrupt flag confirmation.
R/W
R/W
R/W
R/W
Description
I
0: I
1: I
I
0: Disables interrupts from the I
1: Enables interrupts from the I
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode with the I
format. In slave receive mode with I
R/W bit in the first frame immediately after the start
condition sets these bits in receive mode or transmit mode
automatically by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.
2
2
C Bus Interface Enable
C Bus Interface Interrupt Enable
interface module internal state is initialized. SAR and
SARX can be accessed.
operation, and the ports function as the SCL and SDA
input/output pins. ICMR and ICDR can be accessed.
CPU
CPU.
2
2
C bus interface modules are stopped and I
C bus interface modules can perform transfer
2
2
C bus interface to the
C bus interface to the
2
C bus format, the
2
C bus
2
C bus
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