DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 32

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

14.4 Operation .......................................................................................................................... 352
14.5 Interrupt Sources............................................................................................................... 355
14.6 Usage Notes ...................................................................................................................... 356
Section 15 Serial Communication Interface (SCI and IrDA)
15.1 Features ............................................................................................................................. 359
15.2 Input/Output Pins .............................................................................................................. 361
15.3 Register Descriptions ........................................................................................................ 361
15.4 Operation in Asynchronous Mode .................................................................................... 376
15.5 Multiprocessor Communication Function......................................................................... 387
15.6 Operation in Clocked Synchronous Mode ........................................................................ 393
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14.4.1 Watchdog Timer Mode ........................................................................................ 352
14.4.2 Interval Timer Mode ............................................................................................ 354
14.4.3 RESO Signal Output Timing ............................................................................... 355
14.6.1 Notes on Register Access..................................................................................... 356
14.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 357
14.6.3 Changing Values of CKS2 to CKS0 Bits............................................................. 357
14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 357
14.6.5 System Reset by RESO Signal............................................................................. 358
14.6.6 Counter Values during Transitions between High-Speed, Sub-Active,
15.3.1 Receive Shift Register (RSR) .............................................................................. 362
15.3.2 Receive Data Register (RDR) .............................................................................. 362
15.3.3 Transmit Data Register (TDR)............................................................................. 362
15.3.4 Transmit Shift Register (TSR) ............................................................................. 362
15.3.5 Serial Mode Register (SMR)................................................................................ 363
15.3.6 Serial Control Register (SCR).............................................................................. 364
15.3.7 Serial Status Register (SSR) ................................................................................ 366
15.3.8 Serial Interface Mode Register (SCMR).............................................................. 368
15.3.9 Bit Rate Register (BRR) ...................................................................................... 369
15.3.10 Keyboard Comparator Control Register (KBCOMP) .......................................... 375
15.4.1 Data Transfer Format........................................................................................... 377
15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous
15.4.3 Clock.................................................................................................................... 379
15.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 380
15.4.5 Data Transmission (Asynchronous Mode)........................................................... 381
15.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 383
15.5.1 Multiprocessor Serial Data Transmission ............................................................ 388
15.5.2 Multiprocessor Serial Data Reception ................................................................. 390
15.6.1 Clock.................................................................................................................... 393
and Watch Modes ................................................................................................ 358
Mode .................................................................................................................... 378
................................. 359