DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 425

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to
by the CPU at all times.
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Legend:
B:
N: BRR setting for baud rate generator (0
n:
Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the
maximum bit rate settable for each frequency. Table 15.6 shows sample N settings in BRR in
clocked synchronous mode. Tables 15.5 and 15.7 show the maximum bit rates with external clock
input.
Mode
Asynchronous mode
Clocked synchronous mode
:
Operating frequency (MHz)
Determined by the SMR settings shown in the following table.
Bit rate (bit/s)
CKS1
0
0
1
1
Bit Rate Register (BRR)
SMR Setting
CKS0
0
1
0
1
n
0
1
2
3
Bit Rate
B =
B =
64
64
Section 15 Serial Communication Interface (SCI and IrDA)
2
2
2n-1
2n-1
N
10
10
6
6
(N+1)
(N+1)
255)
Rev. 3.00 Mar 21, 2006 page 369 of 788
Error
Error (%) = {
B
64
2
REJ09B0300-0300
10
2n-1
6
(N+1)
– 1 }
100

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