DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 459

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Transmission: During transmission, the output signals from the SCI (UART frames) are
converted to IR frames using the IrDA interface (see figure 15.22).
For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is
output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in
KBCOMP.
The high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%)
(3/16
MHz, a high-level pulse width of at least 1.4 µs to 1.6 µs can be specified.
For serial data of level 1, no pulses are output.
Reception: During reception, IR frames are converted to UART frames using the IrDA interface
before inputting to SCI_2.
Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when
no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 s, the
minimum width allowed, the pulse is recognized as level 0.
bit rate) + 1.08 s at maximum. For example, when the frequency of system clock is 20
Transmission
Figure 15.22 IrDA Transmission and Reception
Start
bit
Bit
cycle
Start
bit
0
0
1
1
0
0
Section 15 Serial Communication Interface (SCI and IrDA)
UART frame
IR frame
1
1
0
0
Data
Data
0
0
Rev. 3.00 Mar 21, 2006 page 403 of 788
Reception
1
1
Pulse width is 1.6 µs to
3/16 bit cycle
1
1
0
0
Stop
bit
Stop
bit
1
1
REJ09B0300-0300
bit rate or