DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 675

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

6. Before branching to the programming control program (H'FFE088 *
7. Boot mode can be cleared by a reset. Cancel the reset *
8. Do not change the mode pin input levels in boot mode. If mode pin input levels are changed
9. All interrupts are disabled during programming or erasing of the flash memory.
Notes: 1. Address area for the H8S/2140B, H8S/2141B, H8S/2148B, H8S/2160B, and
switches to the programming control program. Figure 23.8 shows the on-chip RAM area in
boot mode.
LSI terminates transfer operations by the SCI_1 (by clearing the RE and TE bits in SCR to 0),
but the adjusted bit rate value remains set in BRR. Therefore, the programming control
program can still use it for transfer of write data or verify data with the host. The TxD1 pin is
in high-level output state. The contents of the CPU general registers are undefined immediately
after branching to the programming control program. These registers must be initialized at the
beginning of the programming control program, since the stack pointer (SP), in particular, is
used implicitly in subroutine calls, etc.
at least 20 states, and then setting the mode pins. Boot mode is also cleared when a WDT
overflow occurs.
from low to high during reset, operating modes are switched and the state of ports that are also
used for address output and bus control output signals (AS, RD, and HWR) are changed *
Therefore, set these pins carefully not to be output signals during reset or not to conflict with
LSI external signals.
2. Address area for the H8S/2140B, H8S/2141B, H8S/2148B, H8S/2160B, and
3. RAM address for the H8S/2140B, H8S/2141B, H8S/2148B, H8S/2160B, and
4. After reset is cancelled, mode pin input settings must satisfy the mode programming
5. The ports that also have address output functions output low as address output when
H8S/2161B. On the H8S/2145B, the address area is from H'FFD080 to H'FFD87F.
H8S/2161B. On the H8S/2145B, the address area is from H'FFD080 to H'FFD087.
H8S/2161B. On the H8S/2145B, the address is H'FFD088.
setup time (t
the mode pins are set to mode 1 during a reset. In modes other than mode 1, it enters
the high impedance state. Bus control output signals output high when the mode pins
are set to mode 1 during a reset. In modes other than mode 1, it enters the high
impedance state.
MDS
= 4 states).
Rev. 3.00 Mar 21, 2006 page 619 of 788
4
after driving the reset pin low, waiting
3
in the RAM area), this
REJ09B0300-0300
Section 23 ROM
5
.