DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 527

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

2
Section 16 I
C Bus Interface (IIC) (Optional)
2
Settings of bits other than TRS in ICCR that allow I
C bus format operation
2
Automatic switching is performed from formatless mode to the I
C bus format when the SW bit in
DDCSWR is automatically cleared to 0 on detection of a falling edge on the SCL pin. Switching
2
from the I
C bus format to formatless mode is achieved by setting the SW bit in DDCSWR to 1 by
software.
2
In formatless mode, bits (such as MSL and TRS) that control the I
C bus interface operating mode
2
must not be modified. When switching from the I
C bus format to formatless mode, set the TRS
bit to 1 or clear it to 0 according to the transfer direction (transmission or reception) in formatless
2
mode, then set the SW bit to 1. After automatic switching from formatless mode to the I
C bus
format (slave mode), the TRS bit is automatically cleared to 0 in order to wait for slave address
reception.
2
If a falling edge is detected on the SCL pin during formatless operation, the mode of the I
C bus
2
interface is immediately switched to I
C bus format before a stop condition is detected.
16.4.9
Operation Using DTC
This LSI provides the DTC to allow continuous data transfer. The DTC is initiated when the IRTR
flag is set to 1, which is one of the two interrupt flags (IRTR and IRIC). When the ACKE bit is 0,
the ICDRE, IRIC, and IRTR flags are set at the end of data transmission regardless of the
acknowledge bit value. If the ACKE bit is 1, the ICDRE, IRIC, and IRTR flags are set when data
transmission is completed with the acknowledge bit value of 0, and if the ACKE bit is 1, only the
IRIC flag is set when data transmission is completed with the acknowledge bit value of 1.
When initiated, the DTC transfers specified number of bytes, clears the ICDRE, IRIC, and IRTR
flags to 0. Therefore, no interrupt is generated during continuous data transfer; however, if data
transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, the DTC
is not initiated, thus allowing an interrupt to be generated if enabled.
The acknowledge bit may indicate specific events such as completion of receive data processing
for some receiving devices, and for other receiving devices, the acknowledge bit may be fixed at
1, indicating no specific events.
2
The I
C bus format provides for selection of the slave device and transfer direction by means of
the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out
in conjunction with CPU processing by means of interrupts.
Table 16.7 shows some examples of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Rev. 3.00 Mar 21, 2006 page 471 of 788
REJ09B0300-0300