DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 674

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 23 ROM
Table 23.4 On-Board Programming Mode Settings
Mode Setting
Boot mode
User program
mode
Note:
23.7.1
Table 23.5 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
2. The SCI_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data,
3. When the boot program is initiated, this LSI measures the low-level period of asynchronous
4. After matching the bit rates, this LSI transmits one H'00 byte to the host to indicate the end of
5. In boot mode, a part of the on-chip RAM area is used by the boot program. Addresses
Rev. 3.00 Mar 21, 2006 page 618 of 788
REJ09B0300-0300
the host beforehand. Prepare a programming control program in accordance with the
description in section 23.8, Flash Memory Programming/Erasing. In boot mode, if any data
exists in the flash memory (except in the case that all data are 1), all blocks in the flash
memory are erased. Use boot mode at initial writing in the on-board state, or forced recovery
when user program mode cannot be executed because the program to be initiated in user
program mode was mistakenly erased.
1 stop bit, and no parity.
SCI communication data (H'00) transmitted continuously from the host. This LSI then
calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match
that of the host. The reset should end with the RxD1 pin high. The RxD1 and TxD1 pins
should be pulled up on the board if necessary. After the reset ends, it takes approximately 100
states before this LSI is ready to measure the low-level period.
bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has
been received normally, and transmit one H'55 byte to this LSI. If reception could not be
performed normally, initiate boot mode again by a reset. Depending on the host’s transfer bit
rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates
of the host and this LSI. To operate the SCI properly, set the host’s transfer bit rate and system
clock frequency of this LSI within the ranges listed in table 23.6.
H'FFE080 to H'FFE87F *
from the host. Note, however, that ID codes are assigned to addresses H'FFE080 to
H'FFE087 *
* Can be used as an I/O port after the boot mode activation.
Boot Mode
2
. The boot program area cannot be used until the execution state in boot mode
Mode 2 (advanced mode)
Mode 3 (normal mode)
1
is the area to which the programming control program is transferred
MD1
0
1
1
MD0
0
0
1
P92
1 *
P91
1 *
P90
1 *