DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 531

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
16.5
The IIC has interrupt sources IICI and DDCSWI. Table 16.8 shows the interrupt sources and
priority. Individual interrupt sources can be enabled or disabled using the enable bits in ICCR and
DDCSWR, and are sent to the interrupt controller independently.
An IICI interrupt can activate the DTC to allow data transfer.
Table 16.8 IIC Interrupt Sources
16.6
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
2. Either of the following two conditions will start the next transfer. Pay attention to these
3. Table 16.9 shows the timing of SCL and SDA outputs in synchronization with the internal
Channel
0
1
to generate a stop condition is issued before the start condition is output to the I
condition will be output correctly. To output the start condition followed by the stop condition,
after issuing the instruction that generates the start condition, read DR in each I
pin, and check that SCL and SDA are both low. The pin states can be monitored by reading
DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition.
Note that SCL may not yet have gone low when BBSY is cleared to 0.
conditions when accessing to ICDR.
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
Interrupt Sources
Usage Notes
Name
IICI0
DDCSWI
IICI1
Enable
Bit
IEIC
IE
IEIC
Interrupt Source
I
interrupt request
Format automatic
switch interrupt
I
interrupt request
2
2
C bus interface
C bus interface
Section 16 I
Interrupt
Flag
IRIC
IF
IRIC
Rev. 3.00 Mar 21, 2006 page 475 of 788
2
C Bus Interface (IIC) (Optional)
DTC Activation
Not possible
Possible
Possible
REJ09B0300-0300
2
2
C bus output
C bus, neither
Priority
High
Low

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