DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 522

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 16 I
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations in
slave transmit mode are described below.
1. Initialize slave receive mode and wait for slave address reception.
2. When the slave address matches in the first frame following detection of the start condition,
3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the ICDRE flag is cleared to
4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal.
5. To continue transmission, write the next data to be transmitted into ICDR. The ICDRE flag is
Transmit operations can be performed continuously by repeating steps [4] and [5].
6. Clear the IRIC flag to 0.
7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in
8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode.
9. Dummy-read ICDR to release SDA on the slave side.
Rev. 3.00 Mar 21, 2006 page 466 of 788
REJ09B0300-0300
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If
the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave
transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC
bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the
ICDRE flag is set to 1. The slave device drives SCL low from the fall of the transmit clock
until ICDR data is written, to disable the master device to output the next transfer clock.
0. The written data is transferred to ICDRS, and the ICDRE and IRIC flags are set to 1 again.
The slave device sequentially sends the data written into ICDRS in accordance with the clock
output by the master device.
The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR
register writing to the IRIC flag clearing should be performed continuously. Prevent any other
interrupt processing from being inserted.
As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to
determine whether the transfer operation was performed successfully. When one frame of data
has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock
pulse. When the ICDRE flag is 0, the data written into ICDR is transferred to ICDRS,
transmission starts, and the ICDRE and IRIC flags are set to 1 again. If the ICDRE flag has
been set to 1, this slave device drives SCL low from the fall of the transmit clock until data is
written to ICDR.
cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from
the ICDR register writing to the IRIC flag clearing should be performed continuously. Prevent
any other interrupt processing from being inserted.
the ACKB bit to 0.
2
C Bus Interface (IIC) (Optional)

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