DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 500

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 16 I
16.4.2
Initialize the IIC by the procedure shown in figure 16.7 before starting transmission/reception of
data.
Note: Be sure to modify the ICMR register after transmit/receive operation has been completed.
16.4.3
In I
data, and the slave device returns an acknowledge signal.
Figure 16.8 shows the sample flowchart for the operations in master transmit mode.
Rev. 3.00 Mar 21, 2006 page 444 of 788
REJ09B0300-0300
2
C bus format master transmit mode, the master device outputs the transmit clock and transmit
If the ICMR register is modified during transmit/receive operation, bit counter BC2 to
BC0 will be modified erroneously, thus causing incorrect operation.
<< Start transmit/receive operation >>
Initialization
Master Transmit Operation
2
C Bus Interface (IIC) (Optional)
Set MSTP4 = 0 (IIC_0)
Set IICE = 1 in STCR
Set ICE = 0 in ICCR
Set ICE = 1 in ICCR
Set SAR and SARX
MSTP3 = 0 (IIC_1)
Start initialization
Set DDCSWR
(MSTPCRL)
Set STCR
Set ICMR
Set ICSR
Set ICXR
Set ICCR
Figure 16.7 Sample Flowchart for IIC Initialization
Cancel module stop mode
Enable the CPU accessing to the IIC control register and data register
Set IIC communication format
(SWE, SW, IE, and IF)
Enable SAR and SARX to be accessed
Set the first and second slave addresses and IIC communication format
(SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX)
Enable ICMR and ICDR to be accessed
Use SCL/SDA pin as an IIC port
Set acknowledge bit (ACKB)
Set transfer rate (IICX)
Set communication format, wait insertion, and transfer rate
(MLS, WAIT, CKS2 to CKS0)
Enable interrupt
(STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0)
Set interrupt enable, transfer mode, and acknowledge decision
(IEIC, MST, TRS, and ACKE)