DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 484

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 16 I
Bit Bit Name
1
Note:
When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously
without CPU intervention.
When, with the I
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag (the
DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission
start condition or stop condition after a slave address (SVA) or general call address match in I
bus format slave mode.
Even when the IRIC flag and IRTR flag are set, the ICDRE or ICDRF flag may not be set. The
IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous
Rev. 3.00 Mar 21, 2006 page 428 of 788
REJ09B0300-0300
IRIC
* Only 0 can be written, to clear the flag.
2
C Bus Interface (IIC) (Optional)
2
C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
Initial Value R/W
0
R/(W) * Clocked synchronous serial format and formatless modes:
Description
When the ICDRE or ICDRF flag is set to 1 in any operating
mode:
[Clearing conditions]
At the end of data transfer (rise of the 8th
transmit/receive clock with serial format selected and
rise of the 9th transmit/receive clock with formatless
selected)
When a start condition is detected with serial format
selected
When the SW bit in DDCSWR is set to 1
When a start condition is detected in transmit mode
(when a start condition is detected in transmit mode
and the ICDRE flag is set to 1)
When data is transferred among the ICDR register and
buffer (when data is transferred from ICDRT to ICDRS
in transmit mode and the ICDRE flag is set to 1, or
when data is transferred from ICDRS to ICDRR in
receive mode and the ICDRF flag is set to 1)
When 0 is written in IRIC after reading IRIC = 1
When ICDR is read from or written to by the DTC (This
may not function as a clearing condition depending on
the situation. For details, see the description of the DTC
operation given below.)
2
C