DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 532

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 16 I
Table 16.9 I
Note:
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
5. The I
Rev. 3.00 Mar 21, 2006 page 476 of 788
REJ09B0300-0300
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
therefore depends on the system clock cycle t
Characteristics. Note that the I
system clock frequency of less than 5 MHz.
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 16.10.
* 6t
2
C bus interface specification for the SCL rise time t
2
cyc
C Bus Interface (IIC) (Optional)
2
C Bus Timing (SCL and SDA Outputs)
when IICX is 0, 12t
2
cyc
C bus interface AC timing specifications will not be met with a
when 1.
2
C bus interface monitors the SCL line and synchronizes
Symbol
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
sr
(the time for SCL to go from low to V
cyc
2
C bus interface, the high period of SCL is
, as shown in section 28, Electrical
Output Timing
28t
0.5t
0.5t
0.5t
0.5t
1t
0.5t
1t
1t
3t
SCLO
SCLLO
SCLL
cyc
cyc
SCLO
SCLO
SCLO
SCLO
SCLO
– (6t
to 256t
– 3t
sr
– 1t
– 1t
+ 2t
is 1000 ns or less (300 ns for high-
cyc
cyc
cyc
cyc
cyc
or 12t
cyc
cyc
*)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
See figure
28.29.
IH
) exceeds

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