DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 512

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 16 I
Rev. 3.00 Mar 21, 2006 page 456 of 788
REJ09B0300-0300
User processing
(master output)
(master output)
(master output)
(master output)
(slave output)
(slave output)
User processing
Figure 16.17 Example of Stop Condition Issuance Timing in Master Receive Mode
SCL
SDA
SDA
ICDR
SDA
IRTR
SCL
IRIC
SDA
Master tansmit mode
IRTR
ICDR
IRIC
Data 2
2
[1] TRS cleared to 0
C Bus Interface (IIC) (Optional)
Figure 16.16 Example of Master Receive Mode Operation Timing
Bit 0
8
9
A
IRIC cleard to 0
[4] IRTR=0
[3]
Data 1
[6] IRIC clear
Master receive mode
A
[4] IRTR=1
[7] Set ACKB=1
9
[8] Wait for one clock pulse
[3]
[2] ICDR read
Bit 7
1
(dummy read)
Bit 7
[9] Set TRS=1
1
(MLS = ACKB = 0, WAIT = 1)
(MLS = ACKB = 0, WAIT = 1)
Bit 6
[10] ICDR read (Data 2)
2
Bit 6
2
Bit 5
3
Bit 5
3
Data 3
Data 1
Bit 4
[11] IRIC clear
4
Bit 4
Data 2
4
Bit 3
5
Bit 3
5
Bit 2
6
Bit 2
6
Bit 1
7
Bit 1
Bit 0
7
[6] IRIC clear
(to end wait insertion)
8
Bit 0
[4]IRTR=0
[3]
[14] IRIC clear
8
[13] IRTR=0
[12]
A
A
[15] WAIT cleared
[4] IRTR=1
9
[3]
[5] ICDR read
[12]
[13] IRTR=1
to 0, IRIC clear
9
Bit 7
Data 1
(Data 1)
[17] Stop condition
1
issuance
Bit 6
Data 3
2
Stop condition generation
Data 2
[6] IRIC clear
Bit 5
[16] ICDR read
3
(Data 3)
Bit 4
4
Bit 3
5

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