DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 528

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 16 I
Table 16.7 Examples of Operation Using DTC
Item
Slave address +
R/W bit
transmission/
reception
Dummy data
read
Actual data
transmission/
reception
Dummy data
(H'FF) write
Last frame
processing
Transfer request
processing after
last frame
processing
Setting of
number of DTC
transfer data
frames
16.4.10 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 16.29 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Rev. 3.00 Mar 21, 2006 page 472 of 788
REJ09B0300-0300
2
C Bus Interface (IIC) (Optional)
Master Transmit
Mode
Transmission by
DTC (ICDR write)
—
Transmission by
DTC (ICDR write)
—
Not necessary
1st time: Clearing
by CPU
2nd time: Stop
condition issuance
by CPU
Transmission:
Actual data count
+ 1 (+1 equivalent
to slave address +
R/W bits)
Master Receive
Mode
Transmission by
CPU (ICDR write)
Processing by
CPU (ICDR read)
Reception by
DTC (ICDR read)
—
Reception by
CPU (ICDR read)
Not necessary
Reception: Actual
data count
Slave Transmit
Mode
Reception by
CPU (ICDR read)
—
Transmission by
DTC (ICDR write)
Processing by
DTC (ICDR write)
Not necessary
Automatic clearing
on detection of stop
condition during
transmission of
dummy data (H'FF)
Transmission:
Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Slave Receive
Mode
Reception by CPU
(ICDR read)
—
Reception by DTC
(ICDR read)
—
Reception by CPU
(ICDR read)
Not necessary
Reception: Actual
data count