DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 628

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 19 Host Interface LPC Interface (LPC)
19.4.5
A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a
host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the
serialized interrupt transfer cycle generated by the host or a peripheral function, and a request
signal is generated by the frame corresponding to that interrupt. The timing is shown in figure
19.6.
The serialized interrupt transfer cycle frame configuration is as follows. Two of the states
comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level
at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The
recover state must be driven by the host or slave processor that was driving the preceding state.
Rev. 3.00 Mar 21, 2006 page 572 of 788
REJ09B0300-0300
LCLK
SERIRQ
Drive source
LCLK
SERIRQ
Driver
Legend:
H:
SL: Slave control
R:
Host control
Recovery
Host Interface Serialized Interrupt Operation (SERIRQ)
IRQ14 frame
S
IRQ1
None
SL
or
H
R
T:
S:
I:
T
START
Host controller
Turnaround
Sample
Idle
Start frame
H
IRQ15 frame
S
IRQ15
Figure 19.6 SERIRQ Timing
R
R
T
IOCHCK frame
T
S
None
IRQ0 frame
S
R
None
R
T
T
I
S
IRQ1 frame
IRQ1
Host controller
Stop frame
STOP
H
R
T
R
S
IRQ2 frame
T
None
R
Next cycle
T
START