DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 43

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 11.19 Conflict between OCR Write and Compare-Match
Figure 11.20 Conflict between OCRAR/OCRAF Write and Compare-Match
Section 12 8-Bit Timer (TMR)
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Figure 12.5
Figure 12.6
Figure 12.7
Figure 12.8
Figure 12.9
Figure 12.10 Timing of OVF Flag Setting ................................................................................ 305
Figure 12.11 Timing of Input Capture Operation ..................................................................... 307
Figure 12.12 Timing of Input Capture Signal (Input Capture Signal Is Input during TICRR
Figure 12.13 Input Capture Signal Selection ............................................................................ 308
Figure 12.14 Conflict between TCNT Write and Clear ............................................................ 310
Figure 12.15 Conflict between TCNT Write and Increment..................................................... 311
Figure 12.16 Conflict between TCOR Write and Compare-Match........................................... 312
Section 13 Timer Connection
Figure 13.1
Figure 13.2
Figure 13.3
Figure 13.4
Figure 13.5
Figure 13.6
Figure 13.7
Figure 13.8
Figure 13.9
Section 14 Watchdog Timer (WDT)
Figure 14.1
Figure 14.2
Figure 14.3
Figure 14.4
(When Automatic Addition Function Is Not Used) ............................................. 282
(When Automatic Addition Function Is Used) .................................................... 283
Block Diagram of 8-Bit Timers (TMR_0 and TMR_1)....................................... 288
Block Diagram of 8-Bit Timers (TMR_Y and TMR_X) ..................................... 289
Pulse Output Example.......................................................................................... 301
Count Timing for Internal Clock Input ................................................................ 302
Count Timing for External Clock Input (Both Edges) ......................................... 302
Timing of CMF Setting at Compare-Match......................................................... 303
Timing of Toggled Timer Output by Compare-Match A Signal ......................... 303
Timing of Counter Clear by Compare-Match ...................................................... 304
Timing of Counter Clear by External Reset Input ............................................... 304
and TICRF Read)................................................................................................. 307
Block Diagram of Timer Connection................................................................... 318
Timing Chart for PWM Decoding ....................................................................... 330
Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)............ 331
Timing Chart for Clamp Waveform Generation (CL3 Signal) ............................ 331
Timing Chart for Measurement of IVI Signal and IHI Signal Divided
Waveform Periods ............................................................................................... 334
2fH Modification Timing Chart........................................................................... 335
Fall Modification and IHI Synchronization Timing Chart................................... 337
IVG Signal/IHG Signal/CL4 Signal Timing Chart .............................................. 340
CBLANK Output Waveform Generation ............................................................ 343
Block Diagram of WDT....................................................................................... 346
Watchdog Timer Mode (RST/NMI = 1) Operation ............................................. 353
Interval Timer Mode Operation ........................................................................... 354
OVF Flag Set Timing........................................................................................... 354
Rev. 3.00 Mar 21, 2006 page xli of liv

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