DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 348

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 12 8-Bit Timer (TMR)
Bit
7
6
5
4
3
2
1
0
Rev. 3.00 Mar 21, 2006 page 292 of 788
REJ09B0300-0300
Bit Name Initial Value R/W Description
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
0
0
0
0
0
0
0
0
R/W Compare-Match Interrupt Enable B
R/W Compare-Match Interrupt Enable A
R/W Timer Overflow Interrupt Enable
R/W
R/W
R/W
R/W
R/W
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is set to
1. Note that a CMIB interrupt is not generated by TMR_X,
regardless of the CMIEB value.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is set to
1. Note that a CMIA interrupt is not generated by TMR_X,
regardless of the CMIEA value.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
Selects whether the OVF interrupt request (OVI) is enabled
or disabled when the OVF flag in TCSR is set to 1. Note
that an OVI interrupt is not generated by TMR_X,
regardless of the OVIE value.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled
Counter Clear 1, 0
These bits select the method by which the timer counter is
cleared.
00: Clearing is disabled
01: Cleared on compare-match A
10: Cleared on compare-match B
11: Cleared on rising edge of external reset input
Clock Select 2 to 0
These bits select the clock input to TCNT and count
condition, together with the ICKS1 and ICKS0 bits in STCR.
For details, see table 12.2.