DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 122

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 3 MCU Operating Modes
Bit
2
1
0
3.2.3
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Rev. 3.00 Mar 21, 2006 page 66 of 788
REJ09B0300-0300
Bit Name
NMIEG
HIE
RAME
Serial Timer Control Register (STCR)
Initial Value
0
0
1
R/W
R/W
R/W
R/W
Description
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
1: An interrupt is requested at the rising edge of NMI
Host Interface Enable
Controls CPU access to the host interface registers
(HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2),
the keyboard matrix interrupt and MOS input pull-up
control registers (KMIMR, KMPCR, and KMIMRA), the
8-bit timer (TMR_X and TMR_Y) registers
(TCR_X/TCR_Y, TCSR_X/TCSR_Y,
TICRR/TCORA_Y, TICRF/TCORB_Y,
TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, and
TCORB_X), and the timer connection registers
(TCONRI, TCONRO, TCONRS, and SEDGR).
0: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC
1: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC
RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
input
input
to H'(FF)FFFF, CPU access to 8-bit timer (TMR_X
and TMR_Y) registers and timer connection
registers is permitted
to H'(FF)FFFF, CPU access to host interface
registers and keyboard matrix interrupt and MOS
input pull-up control registers is permitted