DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 252

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 8 I/O Ports
8.9.2
P8DR stores output data for the port 8 pins (P86 to P80).
8.9.3
Note:
Rev. 3.00 Mar 21, 2006 page 196 of 788
REJ09B0300-0300
Bit
7
6
5
4
3
2
1
0
ICE
CKE1
C/A
CKE0
P86DDR
Pin Function
P86/IRQ5/ SCK1/SCL1
The pin function is switched as shown below according to the combination of the CKE1 and
CKE0 bits in SCR of SCI_1, the C/A bit in SMR of SCI_1, the ICE bit in ICCR of IIC_1, and
the P86DDR bit.
* When the IRQ5E bit in IER is set to 1, this pin is used as the IRQ5 input pin. When this
Bit Name
—
P86DR
P85DR
P84DR
P83DR
P82DR
P81DR
P80DR
Port 8 Data Register (P8DR)
Pin Functions
pin is used as the SCL1 I/O pin, bits CKE1 and CKE0 in SCR of SCI_1 and bit C/A in
SMR of SCI_1 must all be cleared to 0. When the P86 output pin and SCK1 output pin
are set, the output type is NMOS push-pull output. SCL1 is an NMOS-only output, and
has direct bus drive capability.
input pin
P86
Initial Value
1
0
0
0
0
0
0
0
0
0
output pin
P86
0
1
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
output pin
SCK1
Description
Reserved
The initial value must not be changed.
If a port 8 read is performed while P8DDR bits are
set to 1, the P8DR values are read directly,
regardless of the actual pin states. If a port 8 read
is performed while P8DDR bits are cleared to 0,
the pin states are read.
—
IRQ5 input pin *
0
1
output pin
SCK1
—
—
1
input pin
SCK1
—
—
—
1
I/O pin
SCL1
—
1
0
0
0