DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 552

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 17 Keyboard Buffer Controller
17.4
17.4.1
In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and
inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity
bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A sample receive
processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4.
Rev. 3.00 Mar 21, 2006 page 496 of 788
REJ09B0300-0300
Operation
Receive Operation
Receive data processing
(receive enabled state)
Receive enabled state
and KDI bits both
Clear KBF flag
Set KBIOE bit
Read KBCRH
Read KBBR
Set KBE bit
KBS = 1?
KBF = 1?
PER = 0?
KCLKI
Start
1?
Figure 17.3 Sample Receive Processing Flowchart
Yes
Yes
Yes
Yes
[1]
[2]
No
[3]
No
No
No
[6]
Keyboard side in data
Execute receive abort
Error handling
transmission state.
[4]
processing.
[5]
[1] Set the KBIOE bit to 1 in
[2] Read KBCRH, and if the
[3] Detect the start bit output
[4] When a stop bit is received,
[5] Perform receive data
[6] Clear the KBF flag to 0 in
The receive operation can be
continued by repeating steps
[3] to [6].
KBCRL.
KCLKI and KDI bits are
both 1, set the KBE bit
(receive enabled state).
on the keyboard side and
receive data in
synchronization with the fall
of KCLK.
the keyboard buffer
controller drives KCLK low
to disable keyboard
transmission (automatic I/O
inhibit).
If the KBIE bit is set to 1 in
KBCRH, an interrupt
request is sent to the CPU
at the same time.
processing.
KBCRL. At the same time,
the system automatically
drives KCLK high, setting
the receive enabled state.

Related parts for DF2148BTE20