DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 356

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 12 8-Bit Timer (TMR)
12.3.6
TICR is an 8-bit register. The contents of TCNT are transferred to TICR at the rising edge of the
external reset input. TICR cannot be directly accessed by the CPU. The TICR function is used for
the timer connection. For details, refer to section 13, Timer Connection.
12.3.7
TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always
compared with TCNT. When a match is detected, a compare-match C signal is generated.
However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of
TICR is disabled. TCORC is initialized to H'FF. The TCORC function is used for the timer
connection. For details, refer to section 13, Timer Connection.
12.3.8
TICRR and TICRF are 8-bit read-only registers. The contents of TCNT are transferred at the
rising edge and falling edge of the external reset input in that order, when the ICST bit in TCONRI
of the timer connection is set to 1. The ICST bit is cleared to 0 when one capture operation ends.
TICRR and TICRF are initialized to H'00. The TICRR and TICRF functions are used for timer
connection. For details, refer to section 13, Timer Connection.
12.3.9
TISR selects a signal source of external clock/reset input for the counter.
Rev. 3.00 Mar 21, 2006 page 300 of 788
REJ09B0300-0300
Bit
7
to
1
0
Bit Name Initial Value R/W
—
IS
Input Capture Register (TICR)
Time Constant Register (TCORC)
Input Capture Registers R and F (TICRR, TICRF)
Timer Input Select Register (TISR)
All 1
0
R/(W)
R/W
Description
Reserved
The initial values should not be modified.
Input Select
Selects an internal synchronization signal (IVG signal) or
timer clock/reset input pin VSYNCI/TMIY (TMCIY/TMRIY)
as the signal source of external clock/reset input for the
TMR_Y counter.
0: IVG signal is selected
1: VSYNCI/TMIY (TMCIY/TMRIY) is selected