DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 15

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Item
16.3.5 I
Register (ICCR)
Table 16.5 Flash and
Transfer States (Slave
Mode)
16.4.4 Master
Receive Operation
Figure 16.12 Example
of Operation Timing in
Master Receive Mode
(MLS = WAIT = 0,
HNDS = 1)
Figure 16.13 Example
of Stop Condition
Issuance Operation
Timing in Master
Receive Mode (MLS =
WAIT = 0, HNDS = 1)
2
C Bus
Page
427, 428 Table amended
430
451
451
Revision (See Manual for Details)
Bit 1 R/W of I
(Before) R/W
Table 16.5 amended
Figure 16.12 amended
User processing
Figure 16.13 amended
MST
0
0
0
0
0
Bit 1
SCL is fixed low until
stop condition is issued
7
[9] IRIC clear
(master output)
(master output)
(slave output)
TRS
1
1
1
1
1
Bit 0
Master transmit mode
ICDRR
ICDRF
SCL
SDA
SDA
IRTR
8
IRIC
BBSY ESTP STOP IRTR
1
1
1
1
1
[11] Set BBSY = 0 and
A
[8]
9
0
0
0
0
0
SCP = 0
(Stop condition instruction issuance)
[1] TRS = 0 clear
A
9
2
0
0
0
0
0
C Bus Interface Interrupt Request Flag
Stop condition generation
(After) R/(W)*
[10] ICDR read
1 /0 *
—
—
—
1 /0 *
SCL is fixed low until ICDR is read
[1] IRIC clear
(Data 3)
2
2
Master receive mode
AASX AL
—
—
—
—
—
Data 3
Bit 7
1
Rev. 3.00 Mar 21, 2006 page xiii of liv
—
0
—
0
0
[2] ICDR read
Bit 6
2
(Dummy read)
AAS
—
0
—
0
0
Bit 5
3
ADZ
0
0
0
0
0
Data 1
Undefined va
Bit 4
4
ACKB ICDRF ICDRE State
0
0
0
0
0
Bit 3
—
—
—
—
—
5
1
0
1
0
1
Transmission end with
ICDRE = 0
ICDR write with the
above state
Transmission end with
ICDRE = 1
ICDR write with the
above state
Automatic data transfer
from ICDRT to ICDRS
with the above state