DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 581

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

18.5
18.5.1
The host interface can issue four interrupt requests to the slave processor: IBF1 to IBF4. They are
input buffer full interrupts for input data registers IDR_1 to IDR_4 respectively. Each interrupt is
enabled when the corresponding enable bit is set.
Table 18.8 Input Buffer Full Interrupts
18.5.2
Bits P45DR to P43DR in the port 4 data register (P4DR) and bits PB1ODR and PB0ODR in the
port B data register (PBODR) can be used as host interrupt request latches. When they are used as
host interrupt request output, set each bit in the data direction register (DDR) of the pin to 1.
The corresponding bits in P4DR are cleared to 0 by the host processor’s read signal (IOR). If CS1
and HA0 are low, when IOR goes low and the host reads ODR_1, HIRQ1 and HIRQ12 are cleared
to 0. If CS2 and HA0 are low, when IOR goes low and the host reads ODR_2, HIRQ11 is cleared
to 0. The corresponding bit in PBODR is cleared to 0 by the host’s read signal (IOR). If CS3 and
HA0 are low, when IOR goes low and the host reads ODR_3, HIRQ3 is cleared to 0. If CS4 and
HA0 are low, when IOR goes low and the host reads ODR_4, HIRQ4 is cleared to 0. To generate
a host interrupt request, normally on-chip firmware writes 1 in the corresponding bit. In processing
the interrupt, the host’s interrupt handling routine reads the output data register (ODR_1, ODR_2,
ODR_3, or ODR_4) and this clears the host interrupt latch to 0.
Table 18.9 indicates how these bits are set and cleared. Figure 18.3 shows the processing in
flowchart form.
Interrupt
IBF1
IBF2
IBF3
IBF4
Interrupt Sources
IBF1, IBF2, IBF3, and IBF4
HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4
Description
Requested when IBFIE1 is set to 1 and IDR_1 is full
Requested when IBFIE2 is set to 1 and IDR_2 is full
Requested when IBFIE3 is set to 1 and IDR_3 is full
Requested when IBFIE4 is set to 1 and IDR_4 is full
Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 525 of 788
REJ09B0300-0300