DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 93

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
2.4.5
The program counter (PC) among CPU internal registers is initialized when reset exception
handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and the
interrupt mask (I) bits in CCR and EXR are set to 1. The other CCR bits and the general registers
are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should
therefore be initialized by an MOV.L instruction executed immediately after a reset.
2.5
The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1
Figure 2.9 shows the data formats of general registers.
Initial Register Values
Data Formats
General Register Data Formats
Data Type
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
Figure 2.9 General Register Data Formats (1)
General Register
RnH
RnL
RnH
RnL
RnH
RnL
MSB
Data Image
7
7
7
7
Upper
6 5 4 3 2
Don’t care
Don’t care
Don’t care
4 3
Rev. 3.00 Mar 21, 2006 page 37 of 788
Lower
1 0
LSB
0
0
0
MSB
7
7
7
7
Upper
6 5 4 3 2
Don’t care
Don’t care
Don’t care
4 3
Lower
REJ09B0300-0300
Section 2 CPU
1 0
LSB
0
0
0

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