DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 501

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 16.8 Sample Flowchart for Operations in Master Transmit Mode
No
No
No
No
No
Write transmit data in ICDR
Write transmit data in ICDR
Read BBSY flag in ICCR
Read IRIC flag in ICCR
Read ACKB bit in ICSR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Read ACKB bit in ICSR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Yes
Set BBSY =1 and
Set BBSY = 0 and
Set MST = 1 and
End of transmission?
SCP = 0 in ICCR
TRS = 1 in ICCR
SCP = 0 in ICCR
Transmit mode?
Initialize IIC
ACKB = 0?
or ACKB = 1?
BBSY = 0?
IRIC = 1?
IRIC = 1?
IRIC = 1?
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1] Initialization
[2] Test the status of the SCL and SDA lines.
[3] Select master transmit mode.
[4] Start condition issuance
[5] Wait for a start condition generation
[6] Set transmit data for the first byte
[7] Wait for 1 byte to be transmitted.
[8] Test the acknowledge bit
[9] Set transmit data for the second and
[10] Wait for 1 byte to be transmitted.
[11] Determine end of tranfer
[12] Stop condition issuance
(slave address + R/W).
(After writing to ICDR, clear IRIC flag
continuously.)
transferred from the slave device.
subsequent bytes.
continuously.)
(After writing to ICDR, clear IRIC flag
Master receive mode
Section 16 I
Rev. 3.00 Mar 21, 2006 page 445 of 788
2
C Bus Interface (IIC) (Optional)
REJ09B0300-0300

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