DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 695

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 24 Clock Pulse Generator
When Subclock Is Not Needed: Do not enable subclock input when the subclock is not needed.
In transiting to power-down mode, if at least two cycles of the
Note on Subclock Usage:
32-kHz clock are not input after the 32-kHz clock input is enabled (EXCLE = 1) until the
SLEEP instruction is executed (power-down mode transition), the subclock input circuit is
not initialized and an error may occur in the microcomputer.
Before power-down mode is entered with using the subclock, at least two cycle of the 32-kHz
clock should be input after the 32-kHz clock input is enabled (EXCLE = 1).
As described in the hardware manual (clock pulse generator/subclock input circuit), when the
subclock is not used, the subclock input should not be enabled (EXCLE = 0).
24.6
Subclock Waveform Forming Circuit
To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided
clock. The sampling frequency is set by the NESEL bit in LPWRCR.
The subclock is not sampled in subactive mode, subsleep mode, or watch mode.
24.7
Clock Select Circuit
The clock select circuit selects the system clock that is used in this LSI.
A clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a
system clock when returning from high-speed mode, medium-speed mode, sleep mode, reset state,
or standby mode.
A subclock input from the EXCL pin is selected as a system clock in subactive mode, subsleep
mode, or watch mode. At this time, modules such as the CPU, TMR_0, TMR_1, WDT_0,
WDT_1, ports, and interrupt controller and their functions operate depending on the SUB. The
count clock and sampling clock for each timer are divided SUB clocks.
Rev. 3.00 Mar 21, 2006 page 639 of 788
REJ09B0300-0300