DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 386

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 13 Timer Connection
13.4.2
The timer connection facility and TMR_X can be used to generate signals with different duty
cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI
signal). Three clamp waveforms can be generated: the CL1 to CL3 signals. In addition, the CL4
signal can be generated using TMR_Y.
The CL1 signal rises simultaneously with the rise of the IHI signal, and when the CL1 signal is
high, the CL2 signal rises simultaneously with the fall of the IHI signal. The fall of both the CL1
and CL2 signals can be specified by TCORA. The rise of the CL3 signal can be specified as
simultaneous with the sampling of the fall of the IHI signal using the system clock, and the fall of
the CL3 signal can be specified by TCORC. The CL3 signal can also fall when the IHI signal
rises.
TCNT in TMR_X is set to count internal clock pulses and to be cleared on the rising edge of the
external reset signal (IHI signal).
The value to be used as the CL1 signal pulse width is written in TCORA. Write a value of H'02 or
more in TCORA when internal clock is selected as the TMR_X counter clock, and a value or
H'01 or more when /2 is selected. When internal clock is selected, the CL1 signal pulse width
is (TCORA set value + 3
this pulse width is greater than the IHI signal pulse width.
The value to be used as the CL3 signal pulse width is written in TCORC. TICR in TMR_X
captures the value of TCNT at the inverse of the external reset signal edge (in this case, the falling
edge of the IHI signal). The timing of the fall of the CL3 signal is determined by the sum of the
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REJ09B0300-0300
IHI signal
PDC signal
TCORB
(threshold)
TCNT
Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation)
Counter reset
caused by
IHI signal
Figure 13.2 Timing Chart for PWM Decoding
IHI signal is tested
at compare-match
0.5). When the CL2 signal is used, the setting must be made so that
Counter clear
caused by
TCNT overflow
At the 2nd compare-match,
IHI signal is not tested