DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 486

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 16 I
Table 16.5 Flags and Transfer States (Slave Mode)
MST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Legend:
0:
1:
—: Previous state retained
0 : Cleared to 0
1 : Set to 1
Notes: 1. Set to 1 when 1 is received as a R/W bit following an address.
Rev. 3.00 Mar 21, 2006 page 430 of 788
REJ09B0300-0300
0-state retained
1-state retained
TRS
0
0
1 /0 *
0
1 /0 *
1
1
1
1
1
1
0
0
0
0
0
2. Set to 1 when the AASX bit is set to 1.
3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0.
1
1
BBSY ESTP STOP IRTR
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
2
C Bus Interface (IIC) (Optional)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 /0 *
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1 *
3
0
0
0
0
1
1 /0 *
1 /0 *
1 /0 *
1 /0 *
2
2
2
2
AASX AL
0
0
0
0
1
0
0
0
0
0
0
0
0
AAS
0
0
1
1
0
0
0
0
0
0
0
ADZ
0
0
0
1
0
0
0
0
0
0
0
0
0
0
ACKB ICDRF ICDRE State
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
Idle state (flag clearing
required)
Start condition detected
SAR match in first frame
(SARX
General call address
match in first frame
(SARX
SARS match in first
frame (SAR
Transmission end (ACKE
= 1 and ACKB =1 )
Transmission end with
ICDRE = 0
ICDR write with the
above state
Transmission end with
ICDRE = 1
ICDR write with the
above state
Automatic data transfer
from ICDRT to ICDRS
with the above state
Reception end with
ICDRF=0
ICDR read with the above
state
Reception end with
ICDRF = 1
ICDR read with the above
state
Automatic data transfer
from ICDRS to ICDRR
with the above state
Stop condition detected
SAR)
H'00)
SARX)

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