DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 346

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 12 8-Bit Timer (TMR)
12.2
Table 12.1 summarizes the input and output pins of the TMR.
Table 12.1 Pin Configuration
Channel
TMR_0
TMR_1
TMR_Y
TMR_X
12.3
The TMR has the following registers. For details on the serial timer control register, refer to
section 3.2.3, Serial Timer Control Register (STCR). For details on timer connection register S,
refer to section 13.3.3, Timer Connection Register S (TCONRS).
Notes: 1. TISR is only for the TMR_Y.
Rev. 3.00 Mar 21, 2006 page 290 of 788
REJ09B0300-0300
Timer counter (TCNT)
Time constant register A (TCORA)
Time constant register B (TCORB)
Timer control register (TCR)
Timer control/status register (TCSR)
Timer input select register (TISR) *
Time constant register C (TCORC) *
Input capture register R (TICRR) *
Input capture register F (TICRF) *
2. TCORC, TICRR, and TICRF are only for the TMR_X.
Register Descriptions
Input/Output Pins
Name
Timer output
Timer clock input
Timer reset input
Timer output
Timer clock input
Timer reset input
Timer clock/reset
input
Timer output
Timer clock/reset
input
Symbol
TMO0
TMCI0
TMRI0
TMO1
TMCI1
TMRI1
VSYNCI/TMIY
(TMCIY/TMRIY)
TMOX
HFBACKI/TMIX
(TMCIX/TMRIX)
2
2
1
2
I/O
Output
Input
Input
Output
Input
Input
Input
Output
Input
Function
Output controlled by compare-match
External clock input for the counter
External reset input for the counter
Output controlled by compare-match
External clock input for the counter
External reset input for the counter
External clock input/external reset
input for the counter
Output controlled by compare-match
External clock input/external reset
input for the counter