DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 621

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19.4.3
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086 * -family CPU. A regular-speed A20 gate signal can be output under
firmware control. The fast A20 gate function that is speeded up by hardware is enabled by setting
the FGA20E bit to 1 in HICR0.
Note: An Intel microprocessor
Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1
command followed by data. When the slave processor (this LSI) receives data, it normally uses an
interrupt routine activated by the IBF1 interrupt to read IDR1. At this time, firmware copies bit 1
of data following an H'D1 command and outputs it at the gate A20 pin.
Fast A20 Gate Operation: The internal state of GA20 output is initialized to 1 when FGA20E =
0. When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. The
state of the P81/GA20 pin can be monitored by reading the GA20 bit in HICR2.
The initial output from this pin will be a logic 1, which is the initial value. Afterward, the host
processor can manipulate the output from this pin by sending commands and data. This function is
only available via the IDR1 register. The host interface decodes commands input from the host.
When an H'D1 host command is detected, bit 1 of the data following the host command is output
from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster
than the regular processing using interrupts. Table 19.3 shows the conditions that set and clear
GA20 (P81). Figure 19.4 shows the GA20 output in flowchart form. Table 19.4 indicates the
GA20 output signal values.
Table 19.3 GA20 (P81) Set/Clear Timing
Pin Name
GA20 (P81)
A20 Gate
Setting Condition
When bit 1 of the data that follows an
H'D1 host command is 1
Section 19 Host Interface LPC Interface (LPC)
Rev. 3.00 Mar 21, 2006 page 565 of 788
Clearing Condition
When bit 1 of the data that follows an
H'D1 host command is 0
REJ09B0300-0300

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