DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 710

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 25 Power-Down Modes
When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of
system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock
oscillation stabilization time has passed, the CPU begins reset exception handling.
If the STBY pin is driven low, the LSI enters hardware standby mode.
25.8
Subsleep Mode
The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in
subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1,
and the PSS bit in TCSR (WDT_1) set to 1.
In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0, TMR_1, WDT_0,
and WDT_1 are also stopped. The contents of the CPU’s internal registers, several on-chip
peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their
values before transition as long as the prescribed voltage is supplied.
Subsleep mode is exited by an interrupt (interrupts by on-chip peripheral modules, NMI, IRQ0 to
IRQ7), the RES pin input, or the STBY pin input.
When an interrupt occurs, subsleep mode is exited and interrupt exception handling starts.
In the case of an IRQ0 to IRQ7 interrupt, subsleep mode is not exited if the corresponding enable
bit has been cleared to 0. In the case of interrupts from the on-chip peripheral modules, subsleep
mode is not exited if the interrupt enable register has been set to disable the reception of that
interrupt, or the interrupt is masked by the CPU.
When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of
system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock
oscillation stabilization time has passed, the CPU begins reset exception handling.
If the STBY pin is driven low, the LSI enters hardware standby mode.
Rev. 3.00 Mar 21, 2006 page 654 of 788
REJ09B0300-0300