DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 600

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 19 Host Interface LPC Interface (LPC)
Table 19.2 Register Selection
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
19.3.4
The IDR registers are 8-bit read-only registers for the slave processor (this LSI), and 8-bit write-
only registers for the host processor. The registers selected from the host according to the I/O
address are shown in the following table. For information on IDR3 selection, see section 19.3.3,
LPC Channel 3 Address Register (LADR3). Data transferred in an LPC I/O write cycle is written
to the selected register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to
indicate whether the written information is a command or data. The initial values of IDR1 to IDR3
are undefined.
Bits 15 to 4
0000 0000 0110
0000 0000 0110
0000 0000 0110
0000 0000 0110
Rev. 3.00 Mar 21, 2006 page 544 of 788
REJ09B0300-0300
Input Data Registers 1 to 3 (IDR1 to IDR3)
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
0
0
1
0
0
1
I/O Address
Bit 2
0
1
0
1
0
0
1
0
0
1
I/O Address
Bit 3
0
0
0
0
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
0
0
1
0
0
1
Bit 2
0
1
0
1
0
0
0
0
1
1
Bit 0
0
0
0
1
1
0
1
1
Bit 1
Bit 0
0
0
0
0
I/O write
I/O write
I/O read
I/O read
I/O write
I/O read
I/O read
Transfer
Cycle
I/O write
Transfer
Cycle
I/O write
I/O write
I/O write
I/O write
IDR3 write, C/D3
IDR3 write, C/D3
Host Register Selection
ODR3 read
STR3 read
TWR0MW write
TWR1 to TWR15 write
TWR0SW read
TWR1 to TWR15 read
Host Register Selection
IDR1 write, C/D1
IDR1 write, C/D1
IDR2 write, C/D2
IDR2 write, C/D2
0
1
0
1
0
1