DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 170

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Interrupt Controller
Determination of Priority: The DTC activation source is selected in accordance with the default
priority order, and is not affected by mask or priority levels. See table 7.1 for the respective
priority.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
Table 5.7 shows the interrupt factor clear control and selection of interrupt factors by specification
of the DTCE bit of DTC's DTCER, and the DISEL bit of DTC's MRB.
Table 5.7
Legend:
O : The relevant interrupt is used. Interrupt source clearing is performed.
o : The relevant interrupt is used. The interrupt source is not cleared.
*: Don’t care
Note: The SCI, IIC, LPC, or A/D converter interrupt source is cleared when the DTC reads or
Rev. 3.00 Mar 21, 2006 page 114 of 788
REJ09B0300-0300
DTCE
0
1
: The relevant interrupt cannot be used.
(The CPU should clear the source flag in the interrupt handling routine.)
writes to the prescribed register, and is not dependent upon the DISEL bit.
Interrupt Source Selection and Clearing Control
Settings
DTC
DISEL
*
0
1
Interrupt Sources Selection/Clearing Control
DTC
O
o
CPU
O
O

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