DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 310

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 10 14-Bit PWM Timer (PWMX)
An example of setting CFS to 1 (basic cycle = resolution (T)
output) is shown as an additional pulse. When CFS is set to 1, the duty ratio of the basic pulse is
determined by the upper eight bits (DA13 to DA6) in DADR, and the position of the additional
pulse is determined by the following six bits (DA5 to DA0) as shown in figure 10.5.
Table 10.4 shows the position of the additional pulse.
Here, the case of DADR = H'0207 (B’0000 0010 0000 0111) is considered. Figure 10.6 shows an
output waveform. Because CFS = 1 and the value of upper eight bits is B’0000 0010, the duty
ratio of the basic pulse is 2/256
Rev. 3.00 Mar 21, 2006 page 254 of 788
REJ09B0300-0300
DA13 DA12 DA11 DA10 DA9
Figure 10.4 Output Waveform (OS = 1, DADR Corresponds to T
t
t
t
H1
f1
H1
t
Figure 10.5 D/A Data Register Configuration when CFS = 1
t
t
H1
f1
H1
Basic pulse duty ratio
= t
+ t
= t
t
+ t
f1
t
f2
f1
H2
f2
H2
= t
= t
+ t
+ t
f3
f3
H3
= ··· = t
H3
= ··· = t
+ ··· + t
+ ··· + t
t
f255
H2
t
f63
H2
a. CFS = 0 [base cycle = resolution (T) × 64]
b. CFS = 1 [base cycle = resolution (T) × 256]
H255
DA8
H63
= t
= t
(T) of high width.
t
f2
t
f2
f64
f256
+ t
+ t
= T× 256
H64
H256
= T× 64
DA7
= T
= T
1 conversion cycle
1 conversion cycle
H
H
DA6
t
H3
t
H3
DA5
DA4
Additional pulse position
t
H255
t
H63
t
DA3
f255
t
256) and OS to 1 (PWMX inverted
f63
DA2
t
H256
DA1
t
H64
t
f256
t
f64
DA0
H
)
CFS
1
1