DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 650

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 21 A/D Converter
21.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 21.3 shows the A/D conversion timing. Table 21.3 indicates
the A/D conversion time.
As indicated in figure 21.3, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in table 21.3.
In scan mode, the values given in table 21.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 256 state (fixed) when CKS = 0 and 128 states
(fixed) when CKS = 1.
Rev. 3.00 Mar 21, 2006 page 594 of 788
REJ09B0300-0300
SPL
). The length of t
Input Sampling and A/D Conversion Time
Address
Write signal
Input sampling
timing
ADF
Legend:
(1)
(2)
t
t
t
D
SPL
CONV
D
: ADCSR write cycle
: ADCSR address
: A/D conversion start delay
: Input sampling time
: A/D conversion time
varies depending on the timing of the write access to ADCSR. The total
(1)
(2)
t D
Figure 21.3 A/D Conversion Timing
t SPL
D
) passes after the ADST bit in ADCSR is set to
t CONV
CONV
) includes t
D
and the input sampling time

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