DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 454

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 15 Serial Communication Interface (SCI and IrDA)
15.6.4
Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart
for serial data reception.
Rev. 3.00 Mar 21, 2006 page 398 of 788
REJ09B0300-0300
Synchronization
clock
Serial data
RDRF
ORER
or output, starts receiving data, and stores the receive data in RSR.
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode
Serial Data Reception (Clocked Synchronous Mode)
RXI interrupt
request
generated
Bit 7
Bit 0
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
1 frame
Bit 7
Bit 0
RXI interrupt
request generated
Bit 1
ERI interrupt request
generated by overrun
error
Bit 6
Bit 7