DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 669

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

23.5.2
FLMCR2 monitors the state of flash memory programming/erasing protection (error protection)
and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to
H'00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software
standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in
FLMCR1 is cleared to 0.
Bit
7
6 to 2 —
1
0
Bit Name
FLER
ESU
PSU
Flash Memory Control Register 2 (FLMCR2)
Initial Value
0
All 0
0
0
R/W
R
R/(W)
R/W
R/W
Description
Flash memory error
Indicates that an error has occurred during flash
memory programming/erasing. When this bit is set
to 1, flash memory goes to the error-protection
state.
For details, see section 23.9.3, Error Protection.
Reserved
The initial values should not be modified.
Erase Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the erase setup state. When it is
cleared to 0, the erase setup state is cancelled. Set
this bit to 1 before setting the E bit in FLMCR1 to 1.
Program Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the program setup state. When it
is cleared to 0, the program setup state is cancelled.
Set this bit to 1 before setting the P bit in FLMCR1
to 1.
Rev. 3.00 Mar 21, 2006 page 613 of 788
REJ09B0300-0300
Section 23 ROM