TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 103

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

PKFC
(0053H)
PK
(0050H)
PKDR
(0094H)
3.5.15
Note: Read-modify-write is prohibited for the register PKFC.
Bit symbol
Read/Write
Reset State
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Port K (PK0 to PK3)
pins output “0”.
LCD controller (LCP0, LLP, LFR and LBCD).
Port K is a 4-bit output port. Resetting sets the output latch PK to “0”, and PK0 to PK3
In addition to functioning as an output port, port K also functions as output pins for an
The above settings are made using the function register PKFC.
Reset
7
7
7
Function control
PK read
Output latch
PKFC write
PK write
6
6
6
Figure 3.5.42 Register for Port K
Port K Function Register
Port K Drive Register
Figure 3.5.41 Port K
LCP0, LLP, LFR, LBCD
Port K Register
92CH21-101
5
5
5
A
B
Selector
S
4
4
4
Output buffer
0: Port
1: LBCD
Input/Output buffer drive register for standby mode
PK3F
PK3D
PK3
0
3
0
1
3
3
0: Port
1: LFR
PK0 (LCP0)
PK1(LLP)
PK2 (LFR)
PK3 (LBCD)
PK2F
PK2D
PK2
0
2
0
1
2
2
R/W
R/W
W
0: Port
1: LLP
PK1F
PK1D
PK1
0
1
0
1
1
1
TMP92CH21
2009-06-19
0: Port
1: LCP0
PK0F
PK0D
PK0
0
0
0
1
0
0