TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 341

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Bit symbol
Read/Write
Reset State
Function
Note: All registers can read-modify-write.
LCDC0L/LCDC0H/LCDC1L/LCDC1H/LCDC2L/LCDC2H/LCDR0L/LCDR0H Register
C area
A area
B area
(Bit23 to 16)
D7
LSARAH
LSARBH
LSARCH
(02AEH)
(02A2H)
(02A8H)
7
3C0000H to
3D0000H to
3E0000H to
40H
40H
40H
3F0000H to
Address
3CFFFFH
3DFFFFH
H
3EFFFFH
3FFFFFH
Start Address Register
D6
(Bit15 to 8)
6
LSARAM
LSARBM
LSARCM
(02ADH)
(02A1H)
(02A7H)
00H
00H
00H
M
Depends on external LCD driver specification.
Depends on external LCD driver specification.
Depends on external LCD driver specification.
Built-in RAM LCDD1
Built-in RAM LCDD2
Built-in RAM LCDD3
Built-in RAM LCDD4
D5
5
92CH21-339
(Bit7 to 1)
Function
LSARAL
LSARBL
LSARCL
(02ACH)
(02A0H)
(02A6H)
00H
00H
00H
L
D4
4
(02AAH)
CMNAH
(02A4H)
CMNBH
(Bit8)
Row Number Setting Register
00H
00H
H
−
D3
3
Chip Enable
LBCD
LCP0
Pin
LLP
LFR
(Bit7 to 0)
(02A3H)
(02A9H)
CMNAL
CMNBL
00H
00H
L
D2
−
2
D1
1
−
−
−
−
TMP92CH21
2009-06-19
D0
0