TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 96

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.5.12
input or output. Resetting sets PF0 to PF2 to be input ports. It also sets all bits of the
output latch register to “1”. In addition to functioning as general-purpose I/O port pins, PF0
to PF2 can also function as the I/O for serial channels 0 and 1. A pin can be enabled for I/O
by writing a “1” to the corresponding bit of the port F function register (PFFC).
general-purpose output port , PF7 can also function as the SDCLK output. Resetting sets
PF7 to be an SDCLK output port.
(1) Port F0 (TXD0, TXD1), F1 (RXD0, RXD1), F2 (SCLK0,
Port F (PF0 to PF2, PF7)
Ports F0 to F2 are 3-bit general-purpose I/O ports. Each bit can be set individually for
Port F7 is a 1-bit general-purpose output port. In addition to functioning as a
SIO1. Each pin is detailed below.
Ports F0 to F2 are general-purpose I/O ports. They also function as either SIO0 or
PF0
PF1
PF2
(Clock input or output)
(SIO0 module)
(Data output)
Direction control
Function control
(Data input)
SIO mode
Output latch
PFCR write
PF read
PFFC write
SCLK0
RXD0
TXD0
PF write
Reset
S
TXD0
TXD1
Figure 3.5.31 Port F0
UART, IrDA mode
92CH21-94
(Clear to send)
(SIO0 module)
(Data output)
(Data input)
RXD0
TXD0
CTS
Selector
Selector
0
S
S
B
A
(Clock input or output)
(SIO1 module)
(Data output)
(Data input)
SIO mode
SCLK1
RXD1
TXD1
PFFC2<PF0F2>
set possible
Open drain
CTS0
SCLK1,
(SIO1 module)
(Clear to send)
(Data output)
UART mode
(Data input)
RXD1
TXD1
CTS
CTS1
1
PF0 (TXD0, TXD1)
TMP92CH21
2009-06-19
)