TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 232

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

USBREADY
(07E6H)
3.10.3.27 USBREADY Register
bit Symbol
Read/Write
Reset State
VDD
INTXX
PortXX
(Pull-up on/off)
Write signal
USBREADY (Bit0)
Note1: External pull-up resistor and control switch are needed with the TMP92CH21.
Note2: The above setting is an example for communication. A specific circuit is required to prevent current flow at
0: Writing to descriptor RAM has finished.
1: Writing to descriptor RAM is enabled.
(However, writing to descriptor RAM is prohibited when connected to host.)
connector detection , no-use, and no connection.
case, UDC disable detecting USB_RESET signal until USBREADY register is written
“0” after release of USB_RESET.
resistor is connected to host in OFF condition, this condition is equivalent condition
with USB_RESET signal by pull-down resistor on the host side. Therefore UDC is not
detected in USB_RESET until “0” is written to USBREADY register
This register informs finishing writing data to descriptor RAM on UDC.
After assigned data to descriptor RAM, write “0” to bit0.
Detect level of VDD signal from USB cable, and execute initialize sequence. In this
If the pull-up resistor on D+ signal is controlled by control signal, when pull-up
USB host
7
GND
15 kΩ
15 kΩ
6
92CH21-230
5
R1 = 1.5 kΩ
Descriptor RAM access
Device ID RAM
Register in USB
4
R2
R3
3
VCC
VSS
PortXX
D+
D−
TMP92CH21
USBREADY registera access
2
UDC
CPU
1
TMP92CH21
2009-06-19
USBREADY
R/W
0
0