TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 415

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.18 16-Bit Timer/Event Counters (TMRB0)
which has the following operation modes:
them with a double buffer structure), a 16-bit capture register, two comparators, a capture
input controller, a timer flip-flop and a control circuit.
The TMP92CH21 incorporates one multifunctional 16-bit timer/event counter (TMRB0)
The timer/event counter consists of a 16-bit up counter, two 16-bit timer registers (one of
The timer/event counter is controlled by an 11-byte control SFR.
This chapter includes the following sections:
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•
•
3.18.1 Block Diagrams
3.18.2 Operation of Each Block
3.18.3 SFRs
3.18.4 Operation in Each Mode
(1) 16-bit interval timer mode
(2) 16-bit programmable pulse generation (PPG) output mode
16-bit interval timer mode
16-bit event counter mode
16-bit programmable pulse generation (PPG) mode
Spec.
(Address)
External
SFR
pins
Table 3.18.1 Pins and SFR of TMRB0
External clock/capture trigger
input pins
Timer flip-flop output pins
Timer run register
Timer mode register
Timer flip-flop control register
Timer register
Capture register
92CH21-413
Channel
TB0OUT0 (also used as PC2)
TB0RG1H (118BH)
TB0CP0H (118DH)
TB0FFCR (1183H)
TB0RG0H (1189H)
TB0RG1L (118AH)
TB0CP1H (118FH)
TB0RG0L (1188H)
TB0CP0L (118CH)
TB0CP1L (118EH)
TB0MOD (1182H)
TB0RUN (1180H)
TMRB0
None
TMP92CH21
2009-06-19