TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 177

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

BR0CR
(1203H)
BR0ADD
(1204H)
+(16 − K)/16 division enable
BR0ADD
<BR0K3:0>
Note1:Availability of +(16-K)/16 division function
Note2:Set BR0CR <BR0ADDE> to 1 after setting K (K = 1 to 15) to BR0ADD<BR0K3:0> when +(16-K)/16 division function is
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
0
1
Disable
Enable
1111 (K = 15)
0001 (K = 1)
The baud rate generator can be set to “1” in UART mode only when the +(16-K)/16 division function is not used. Do not
used. Writes to unused bits in the BR0ADD register do not affect operation, and undefined data is read from these
unused bits.
use in I/O interface mode.
Figure 3.9.11 Baud Rate Generator Control (Channel 0, BR0CR, BR0ADD)
0000
BR0CR
<BR0S3:0>
to
Always
write “0”.
N
2 to 15
1 , 16
Sets baud rate generator frequency divisor
7
7
−
0
0000 (N = 16)
0001 (N = 1)
+(16 − K)/16
division
0: Disable
1: Enable
BR0ADDE
BR0CR<BR0ADDE> = 1
Disable
Disable
or
6
6
0
UART mode
○
×
00: φT0
01: φT2
10: φT8
11: φT32
N + (16 − K)/16
BR0CK1
Setting the input clock of baud rate generator
1111 (N = 15)
0010 (N = 2)
Divided by
00
01
10
11
Disable
5
5
0
92CH21-175
to
Internal clock φT0
Internal clock φT2
Internal clock φT8
Internal clock φT32
I/O mode
BR0CK0
×
×
BR0CR<BR0ADDE> = 0
4
4
0001 (N = 1) (Only UART)
0
R/W
1111 (N = 15)
0000 (N = 16)
Divided by N
BR0S3
BR0K3
to
3
3
0
0
(divided by N + (16 − K)/16).
Sets frequency divisor “K”
Divided frequency setting
BR0S2
BR0K2
2
2
0
0
R/W
BR0S1
BR0K1
1
1
0
0
TMP92CH21
2009-06-19
BR0S0
BR0K0
0
0
0
0