TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 178

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

BR1CR
(120BH)
BR1ADD
(120CH)
+ (16 − K)/16 division enable
BR1ADD
<BR1K3:0>
Note1:Availability of +(16-K)/16 division function
Note2:Set BR1CR <BR1ADDE> to 1 after setting K (K = 1 to 15) to BR1ADD<BR1K3:0> when the +(16-K)/16 division
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
0
1
Disabled
Enabled
1111 (K = 15)
0001 (K = 1)
The baud rate generator can be set “1” in UART mode only when the +(16-K)/16 division function is not used. Do not
function is used. Writes to unused bits in the BR1ADD register do not affect operation, and undefined data is read from
these unused bits.
use in I/O interface mode.
Figure 3.9.12 Baud Rate Generator Control (Channel 1, BR1CR, BR1ADD)
0000
BR1CR
<BR1S3:0>
to
Always
write “0”.
N
2 to 15
1 , 16
Baud rate generator frequency divisor setting
7
−
0
7
+ (16 − K)/16
division
0: Disable
1: Enable
0000 (N = 16)
0001 (N = 1)
BR1ADDE
BR1CR<BR1ADDE> = 1
Disable
Disable
6
0
or
6
UART mode
○
×
00: φT0
01: φT2
10: φT8
11: φT32
N + (16 − K)/16
BR1CK1
Input clock selection for baud rate generator
1111 (N = 15)
0010 (N = 2)
Divided by
00
01
10
11
Disable
5
0
5
92CH21-176
to
Internal clock φT0
Internal clock φT2
Internal clock φT8
Internal clock φT32
I/O mode
BR1CK0
×
×
BR1CR<BR1ADDE> = 0
4
4
0001 (N = 1) (Only UART)
0
R/W
1111 (N = 15)
0000 (N = 16)
Divided by N
BR1S3
BR1K3
to
3
3
0
0
(divided by N + (16 − K)/16).
Divided frequency setting
Set frequency divisor K
BR1S2
BR1K2
2
0
2
0
R/W
BR1S1
BR1K1
1
0
1
0
TMP92CH21
2009-06-19
BR1S0
BR1K0
0
0
0
0